Typical polar digital power amplifiers (DPAs) employ unit-cells operated in class-E or D-1, denoting a switched-resistance operation which degrades linearity. Besides introducing higher demand on digital predistortion (DPD), it also requires extra quantization bits, impacting the overall efficiency and system complexity. To address this, the present work makes use of an optimized constant-current cascode unit-cell which is combined with reduced conduction angle to achieve linear and efficient operation, while minimizing the effort on DPD and/or calibration. A design strategy is developed which focuses on the cascode bias voltage and transistor relative dimensions as design parameters, allowing cascode efficiency optimization without compromising linearity or reliability. A single-ended polar switched constant-current DPA is implemented in 180-nm standard CMOS. Continuous-wave measurements performed at 800 MHz demonstrate an output power of 24 dBm with a PAE of 47%. The DPA dynamic behavior was tested with a 64-QAM signal with 10 MS/s, achieving an average PAE of 20.9% with a peak-to-average power ratio (PAPR) of 8.7 dB and adjacent-channel leakage ratio (ACLR) = 40.34 dB. These results demonstrate comparable performance with the prior art while using only 6-bits clocked at 100 MHz baseband sampling frequency.