Abstract

Current generation of Noisy Intermediate-Scale Quantum devices is mainly limited by noise, thus making Quantum Error Correction (QEC) mechanisms of paramount importance. QEC is carried out through classical computing architectures, and Field Programmable Gate Arrays (FPGAs) represent a promising platform on which deploying decoding algorithms. Nevertheless, accelerating QEC with FPGAs is a largely unexplored topic in the State of the Art, making it urgent to clearly define the requirements that these designs must satisfy. For this reason, in this work, we analyze literature solutions for FPGA-based QEC and identify the mandatory Key Performance Indicators (KPIs) to address when developing FPGA designs for this task. These KPIs are crucial to guide future research and unleash the full computing power of quantum devices.