Abstract

Advanced packaging has become an important part of the semiconductor technology to realize More-than-Moore paradigm, through its various building blocks for heterogeneous integration 1 . Hybrid bonding has particularly attracted interest from both academics and industry owing to its benefits, such as enabling smaller CD and pitch with passive / active interposer, in contrast to a larger footprint in the traditional microbump approach 2 . Depending on its targeted product application, hybrid bonding requires the right pairing of dielectric and metal, and as such, considerable efforts have been made to explore better dielectrics 2,3 and metallization 4 schemes. The formation of this hybrid dielectric-metal bonding interface is controlled by CMP process, and consequently, there are stringent CMP output requirements to be met, such as surface roughness 2 , metal dishing 5 , and dielectric rounding 6 .In this work, we devise a chip-to-wafer (C2W) test vehicle to explore two types of low temperature dielectrics (Si x O y & Si x N y ) 7 and two types of Cu (conventional and nt-Cu) 4,8 for hybrid bonding integration. We develop a single CMP process with a combination of the two dielectric materials and the two Cu materials. We further validate the impact of the dielectric/metal combinations by carrying out C2W hybrid bonding at various annealing temperatures ranging from 250°C to 350°C and measure its electrical performance 8,9 , such as daisy chain resistance, contact resistance, and leakage current. Finally, we examine the electrical reliability based on JEDEC-standard thermal cycling (TC) to map out the suitability/combination of these materials for different temperature packaging applications.